I was looking just at the boot code. Rockchip has all open source silicon and board code, including the RK3399 https://github.com/coreboot/coreboot/blob/master/src/soc/roc... for memory init. This is the logic typically held back by many other ARM vendors, like Mediatek and Qualcomm, as blobs. There's a pretty interesting diagram showing the blobs in Intel, AMD, Qualcomm, and Mediatek coreboot implementations in figure 5-4 of https://link.springer.com/chapter/10.1007/978-1-4842-7939-7_.... A more cartoonish variant of the figure (but one that's not behind a paywall) can be found in slide 2 of https://osfw.foundation/slides/SiliconInterfaceDesign/OSFF-W.... You're right. Coreboot has open source board code and some open source silicon code for all of the vendors w/ binary boot blobs. So it's not so completely closed. The blobs are usually SOC-specific, board-independent code flows that 'should' just drop in and work.
Note that ram init in VisionFive 2 is done within u-boot SPL, which is loaded into cache-as-ram from the selected (microswitches on the board) boot device.
The non-rewritable ROM inside the SoC does just take care of reading the microswitches and fetching u-boot SPL (or oreboot, an alternative early bootloader in the works).
Remarkably, the boot selection can be UART. This small ROM has an XMODEM implementation for receiving the early bootloader.
u-boot SPL does then check the microswitches again for where to fetch the next stage, which is usually opensbi with u-boot as bundled payload.
