Yes, but pretty much all the information about how the "M1386SX" core handles SMM is contained on that single page, the following ones only describe I/O ports. And it leaves a lot of questions unanswered, like how to access the "GR" registers (something like MSRs on Pentium+?), or the other descriptor caches that aren't saved automatically.

The text is written as if these were standard features of the architecture, or at least documented elsewhere (maybe they were, but can't find anything online now).